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Well, I have beem shocked by these 2gb set during these couple days when I do the quality check for Team Group Micron 5bf
and Samsung UCCC modules. The reason I start this thread is share the information about the oc performance and my personal thoughts regarding the settings on the specific date code UCCC ic.
Basically, I checked all the 20 sets of Team Group UCCC here, actually I accidentally clear cmos after I checked 5bf; then I plug the UCCC set in, key in all the timings I need then check basic official timings. After I done for DDR500, I tried the DDR560 , here we go, I forgot I will need to change the trp to 4 since official timing for this set is 3-4-3-8, 2.65v~2.8v! Since most of Samsung IC doesn't require that much juice, so, I just keep it around 2.65~2.7v.
After boot into windows, I was still not aware of my timing setting is ddr560 3-4-3-8, so I ran the super pi mod 8m first,
well, at that moment when I ran the CPUZ and a64tweakers, I then noticed that I got 3-4-3-8. I thought this must be something wrong, but, it was really on 1t command and everything just all right. so I kept the setting and ran for 32m. Wow it just passed all the way up to DDR570(285) with only 0.02v increasd and couple parameters adjusted. I also did pass the windows memtest 900mb 1500% (1725 cycles) more test for at least about 90 minutes. After this set test, I check all the sets around here, they all did about the same.
well it doesn't mean just team group UCCC can do this, I am just wondering if all the UCCC usersalreay figured this out with about the 0552~0603 dated UCCC. And the chance for doing DDR600 3-4-4-8 on this kind of UCCC is very very greater than earlier batch.
**Again, these UCCC setes are NOT cherry picked; they all ready to ship to retail.;)
So below is my personal settings share with you guys, those settings on this example pretty much can go up to DDR570 if your CPU memory controller and power supply are strong enough.
Now let's go ahead and check the stability tests.
DDR560 3-4-3-6, 2.67v; please see above example.
Digital camera photos during rinning super pi 32m:
DDR570 3-4-3-6, 2.69v
windows screen captured after finished:)
now, here I will strongly recommand that everyone should run memtest windows version instead of DOS version.
1725 cycles and 900mb used memory allocation with at least 1500% passed.:)
Thank you for reading, if needed, I will update some 3d action or other benches later.
Good luck
OPB
and Samsung UCCC modules. The reason I start this thread is share the information about the oc performance and my personal thoughts regarding the settings on the specific date code UCCC ic.
Basically, I checked all the 20 sets of Team Group UCCC here, actually I accidentally clear cmos after I checked 5bf; then I plug the UCCC set in, key in all the timings I need then check basic official timings. After I done for DDR500, I tried the DDR560 , here we go, I forgot I will need to change the trp to 4 since official timing for this set is 3-4-3-8, 2.65v~2.8v! Since most of Samsung IC doesn't require that much juice, so, I just keep it around 2.65~2.7v.
After boot into windows, I was still not aware of my timing setting is ddr560 3-4-3-8, so I ran the super pi mod 8m first,
well, at that moment when I ran the CPUZ and a64tweakers, I then noticed that I got 3-4-3-8. I thought this must be something wrong, but, it was really on 1t command and everything just all right. so I kept the setting and ran for 32m. Wow it just passed all the way up to DDR570(285) with only 0.02v increasd and couple parameters adjusted. I also did pass the windows memtest 900mb 1500% (1725 cycles) more test for at least about 90 minutes. After this set test, I check all the sets around here, they all did about the same.
well it doesn't mean just team group UCCC can do this, I am just wondering if all the UCCC usersalreay figured this out with about the 0552~0603 dated UCCC. And the chance for doing DDR600 3-4-4-8 on this kind of UCCC is very very greater than earlier batch.
**Again, these UCCC setes are NOT cherry picked; they all ready to ship to retail.;)
So below is my personal settings share with you guys, those settings on this example pretty much can go up to DDR570 if your CPU memory controller and power supply are strong enough.
Now let's go ahead and check the stability tests.
DDR560 3-4-3-6, 2.67v; please see above example.
Digital camera photos during rinning super pi 32m:
DDR570 3-4-3-6, 2.69v
windows screen captured after finished:)
now, here I will strongly recommand that everyone should run memtest windows version instead of DOS version.
1725 cycles and 900mb used memory allocation with at least 1500% passed.:)
Thank you for reading, if needed, I will update some 3d action or other benches later.
Good luck
OPB
