[OPB]啥都500玩的很累,來點新鮮的, e8400 空冷600fsb達成
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Ln2倒是沒關係
有趣的當然是DDRIII
重點不在於D-II or D-III
ddr-III可以跑比較多(涵蓋所有DDRII不能跑到的)
所以也比較靈活
所以這是你cpu的fsb極限
加上你已經用LN2,那也夠本了跑不上那是當然
你用ddr2跑跑看能跑空冷那才是屌;)
- 已加入
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我知道這是英文,但是請原諒狂少翻譯功力之差...
只能這漾講
CPU/NB GTL Voltage Reference: CPU: Auto, 0.63x, 0.61x, 0.59x, and 0.57x. NB: Auto, 0.67x, and 0.61x. CPU Gunning Transceiver Logic (GTL) voltages are nothing more than reference levels that the CPU uses when determining if a data or address signal is either high (1) or low (0). Precision voltage dividers generate these voltages and are usually specified as a percentage of VTT. In the case of 0.67, this would be 67% of VTT. For example, if VTT is 1.20v then a CPU GTL Voltage Reference of 0.67x would result in a GTLREF value of 0.67 x 1.20V = ~0.80V.
在Asus的狀況我也跟大家借chris文章說一下
These reference values are particularly important when overclocking quad-core CPUs, especially when venturing above about 450FSB. The ability to tune these values per die can mean the difference between 475FSB and 500FSB. Unfortunately, ASUS' implementation of this functionality is rather incomplete as manipulation of only a single GTLREF value is possible (and in a somewhat imprecise manner). The real power in GTLREF tuning comes in the ability to provide each quad-core die with separate reference values. (Recall that current quad-cores are an MCM consisting of two dual-core dies on a single package.)
好友Praz也說過一些
VTT is the termination voltage. It is also the voltage VREF is derived from.
VTT(min) is the minimum termination voltage.
VREF is the reference voltage. Normally 2/3(VTT)
VIH (min) is the minimum specified valid input high level voltage. For this example it is 100mV above the reference voltage.
VIL (max) is the maximum specified valid input low level voltage. For this example it is 100mV below the reference voltage.
VOH (min) is the minimum output high level voltage. VOH(min) is equal to VTT(min).
VOL (max) is the maximum output low level voltage. This value is equal to 1/3(VTT).
VTT sets the base voltage levels between ground and itself for the entire GTL circuit with the exception of the threshold voltage. VOL (max) is VTT(1/3) and VREF is VTT(2/3). A change to VTT also changes all the other voltage limits of the circuit. Increasing VTT not only strengthens the signal but also acts as a rather course control for what GTL Reference voltage is normally used for.
Overshoot (sometimes referred to as undershoot for falling transitions), is the amount by which the signal's voltage level extends above or below VTT or ground. Limiting overshoot is necessary to insure the flight time meets the design requirements and to avoid damaging the components connected on the GTL bus
Ringback is the amount by which a signal rebounds below the logic high lower limit (or above the logic low upper limit) after an overshoot event has occurred. Ringback must be limited to prevent inadvertent false switching of these digital signals.
Settling time is a measurement of oscillations on the GTL waveform (usually caused by reflections on the transmission line traces). This term measures the amount of time required for oscillations to dampen to a level that will not increase the flight time of the next transition.
GTL designs like most electronic circuits are optimized for a particular range of operating parameters. This is complicated by the fact that the majority of the circuitry is contained in the processor and chipset. Intel designs these circuits for stock operating speeds and voltages. Motherboards built with overclocking in mind can have this point of optimization shifted somewhat by the board manufacturer with board component selection and design. However there is a limitation to what the manufacturers can accomplish. Not only does the board still need to be stable at stock speeds but well below stock if such options as C1E are utilized. The board also has to come in at a predetermined price-point.
Most GTL designs are built around a differential amplifier that is used as a comparator. A differential amplifier is capable of outputting a preset voltage based on two input voltages. A differential amplifier is used because of its narrow threshold regions ensuring a sufficient noise margin with respect to output swing. One input is tied to VREF. This voltage is what the input is compared to and also is what VIH(min) and VIL(max) (VREF +/- the Threshold voltage) are derived from. The other input receives the incoming signal. If the voltage is below VIL(max) it is considered a logic low and if it is above VIH(min) it is a logic high. Based on these inputs the output will be equal to either VTT or ground. The input side of the differential amplifier is called the receiver and the output side is the driver.
GTL circuits are based on an open-drain output. An open-drain output is one that either sinks current or is at a high impedance. It is never the source of current. The output is connected to VTT through the termination resistor. When the output is in a low (logic 0) state it provides a path to ground for VTT and the bus is pulled low. When the output signal is required to be high (logic 1) the output stops conducting current and the bus returns to the voltage level of VTT. Two of the advantages of an open-drain configuration are its low-power requirement by not having to supply the high state current and the ability of multiple devices to communicate on the same bus.
只能這漾講
CPU/NB GTL Voltage Reference: CPU: Auto, 0.63x, 0.61x, 0.59x, and 0.57x. NB: Auto, 0.67x, and 0.61x. CPU Gunning Transceiver Logic (GTL) voltages are nothing more than reference levels that the CPU uses when determining if a data or address signal is either high (1) or low (0). Precision voltage dividers generate these voltages and are usually specified as a percentage of VTT. In the case of 0.67, this would be 67% of VTT. For example, if VTT is 1.20v then a CPU GTL Voltage Reference of 0.67x would result in a GTLREF value of 0.67 x 1.20V = ~0.80V.
在Asus的狀況我也跟大家借chris文章說一下
These reference values are particularly important when overclocking quad-core CPUs, especially when venturing above about 450FSB. The ability to tune these values per die can mean the difference between 475FSB and 500FSB. Unfortunately, ASUS' implementation of this functionality is rather incomplete as manipulation of only a single GTLREF value is possible (and in a somewhat imprecise manner). The real power in GTLREF tuning comes in the ability to provide each quad-core die with separate reference values. (Recall that current quad-cores are an MCM consisting of two dual-core dies on a single package.)
好友Praz也說過一些
VTT is the termination voltage. It is also the voltage VREF is derived from.
VTT(min) is the minimum termination voltage.
VREF is the reference voltage. Normally 2/3(VTT)
VIH (min) is the minimum specified valid input high level voltage. For this example it is 100mV above the reference voltage.
VIL (max) is the maximum specified valid input low level voltage. For this example it is 100mV below the reference voltage.
VOH (min) is the minimum output high level voltage. VOH(min) is equal to VTT(min).
VOL (max) is the maximum output low level voltage. This value is equal to 1/3(VTT).
VTT sets the base voltage levels between ground and itself for the entire GTL circuit with the exception of the threshold voltage. VOL (max) is VTT(1/3) and VREF is VTT(2/3). A change to VTT also changes all the other voltage limits of the circuit. Increasing VTT not only strengthens the signal but also acts as a rather course control for what GTL Reference voltage is normally used for.
Overshoot (sometimes referred to as undershoot for falling transitions), is the amount by which the signal's voltage level extends above or below VTT or ground. Limiting overshoot is necessary to insure the flight time meets the design requirements and to avoid damaging the components connected on the GTL bus
Ringback is the amount by which a signal rebounds below the logic high lower limit (or above the logic low upper limit) after an overshoot event has occurred. Ringback must be limited to prevent inadvertent false switching of these digital signals.
Settling time is a measurement of oscillations on the GTL waveform (usually caused by reflections on the transmission line traces). This term measures the amount of time required for oscillations to dampen to a level that will not increase the flight time of the next transition.
GTL designs like most electronic circuits are optimized for a particular range of operating parameters. This is complicated by the fact that the majority of the circuitry is contained in the processor and chipset. Intel designs these circuits for stock operating speeds and voltages. Motherboards built with overclocking in mind can have this point of optimization shifted somewhat by the board manufacturer with board component selection and design. However there is a limitation to what the manufacturers can accomplish. Not only does the board still need to be stable at stock speeds but well below stock if such options as C1E are utilized. The board also has to come in at a predetermined price-point.
Most GTL designs are built around a differential amplifier that is used as a comparator. A differential amplifier is capable of outputting a preset voltage based on two input voltages. A differential amplifier is used because of its narrow threshold regions ensuring a sufficient noise margin with respect to output swing. One input is tied to VREF. This voltage is what the input is compared to and also is what VIH(min) and VIL(max) (VREF +/- the Threshold voltage) are derived from. The other input receives the incoming signal. If the voltage is below VIL(max) it is considered a logic low and if it is above VIH(min) it is a logic high. Based on these inputs the output will be equal to either VTT or ground. The input side of the differential amplifier is called the receiver and the output side is the driver.
GTL circuits are based on an open-drain output. An open-drain output is one that either sinks current or is at a high impedance. It is never the source of current. The output is connected to VTT through the termination resistor. When the output is in a low (logic 0) state it provides a path to ground for VTT and the bus is pulled low. When the output signal is required to be high (logic 1) the output stops conducting current and the bus returns to the voltage level of VTT. Two of the advantages of an open-drain configuration are its low-power requirement by not having to supply the high state current and the ability of multiple devices to communicate on the same bus.
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pcc0905
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我知道這是英文,但是請原諒狂少翻譯功力之差...
只能這漾講
CPU/NB GTL Voltage Reference: CPU: Auto, 0.63x, 0.61x, 0.59x, and 0.57x. NB: Auto, 0.67x, and 0.61x. CPU Gunning Transceiver Logic (GTL) voltages are nothing more than reference levels that the CPU uses when determining if a data or address signal is either high (1) or low (0). Precision voltage dividers generate these voltages and are usually specified as a percentage of VTT. In the case of 0.67, this would be 67% of VTT. For example, if VTT is 1.20v then a CPU GTL Voltage Reference of 0.67x would result in a GTLREF value of 0.67 x 1.20V = ~0.80V.
在Asus的狀況我也跟大家借chris文章說一下
These reference values are particularly important when overclocking quad-core CPUs, especially when venturing above about 450FSB. The ability to tune these values per die can mean the difference between 475FSB and 500FSB. Unfortunately, ASUS' implementation of this functionality is rather incomplete as manipulation of only a single GTLREF value is possible (and in a somewhat imprecise manner). The real power in GTLREF tuning comes in the ability to provide each quad-core die with separate reference values. (Recall that current quad-cores are an MCM consisting of two dual-core dies on a single package.)
好友Praz也說過一些
VTT is the termination voltage. It is also the voltage VREF is derived from.
VTT(min) is the minimum termination voltage.
VREF is the reference voltage. Normally 2/3(VTT)
VIH (min) is the minimum specified valid input high level voltage. For this example it is 100mV above the reference voltage.
VIL (max) is the maximum specified valid input low level voltage. For this example it is 100mV below the reference voltage.
VOH (min) is the minimum output high level voltage. VOH(min) is equal to VTT(min).
VOL (max) is the maximum output low level voltage. This value is equal to 1/3(VTT).
VTT sets the base voltage levels between ground and itself for the entire GTL circuit with the exception of the threshold voltage. VOL (max) is VTT(1/3) and VREF is VTT(2/3). A change to VTT also changes all the other voltage limits of the circuit. Increasing VTT not only strengthens the signal but also acts as a rather course control for what GTL Reference voltage is normally used for.
Overshoot (sometimes referred to as undershoot for falling transitions), is the amount by which the signal's voltage level extends above or below VTT or ground. Limiting overshoot is necessary to insure the flight time meets the design requirements and to avoid damaging the components connected on the GTL bus
Ringback is the amount by which a signal rebounds below the logic high lower limit (or above the logic low upper limit) after an overshoot event has occurred. Ringback must be limited to prevent inadvertent false switching of these digital signals.
Settling time is a measurement of oscillations on the GTL waveform (usually caused by reflections on the transmission line traces). This term measures the amount of time required for oscillations to dampen to a level that will not increase the flight time of the next transition.
GTL designs like most electronic circuits are optimized for a particular range of operating parameters. This is complicated by the fact that the majority of the circuitry is contained in the processor and chipset. Intel designs these circuits for stock operating speeds and voltages. Motherboards built with overclocking in mind can have this point of optimization shifted somewhat by the board manufacturer with board component selection and design. However there is a limitation to what the manufacturers can accomplish. Not only does the board still need to be stable at stock speeds but well below stock if such options as C1E are utilized. The board also has to come in at a predetermined price-point.
Most GTL designs are built around a differential amplifier that is used as a comparator. A differential amplifier is capable of outputting a preset voltage based on two input voltages. A differential amplifier is used because of its narrow threshold regions ensuring a sufficient noise margin with respect to output swing. One input is tied to VREF. This voltage is what the input is compared to and also is what VIH(min) and VIL(max) (VREF +/- the Threshold voltage) are derived from. The other input receives the incoming signal. If the voltage is below VIL(max) it is considered a logic low and if it is above VIH(min) it is a logic high. Based on these inputs the output will be equal to either VTT or ground. The input side of the differential amplifier is called the receiver and the output side is the driver.
GTL circuits are based on an open-drain output. An open-drain output is one that either sinks current or is at a high impedance. It is never the source of current. The output is connected to VTT through the termination resistor. When the output is in a low (logic 0) state it provides a path to ground for VTT and the bus is pulled low. When the output signal is required to be high (logic 1) the output stops conducting current and the bus returns to the voltage level of VTT. Two of the advantages of an open-drain configuration are its low-power requirement by not having to supply the high state current and the ability of multiple devices to communicate on the same bus.
...
這600fsb真的是很珍貴的經驗，
雖然我只是要追求穩定的333fsb，
但是這解說真的很棒！
PSU電流的"效率"也是上高外頻"穩定"的重點，
真是一針見血。
