引用一下Tomshardware的文章
Integrated Memory Interface: No Northbridge Meddling
The concept of the Hammer multi-processor systems includes local memory on each CPU so that the other CPUs can access the memory of these CPUs via the HyperTransport bus. Initially, only the server version of the Hammer, the Opteron, will be equipped with two 72-bit wide DDR SDRAM channels. With a total of eight DIMM slots, this allows each processor to address 8 GB. The dual-channel interface of the Athlon 64 FX-51 offers a memory bandwidth of 6.4 GB/s. Still, the integration of the memory controller can also be considered as a limitation on flexibility.
HyperTransport: A High-speed Bus Without Detours
Unlike all Intel CPUs, which communicate with the Northbridge via a regular parallel FSB, AMD's Hammer relies on a HyperTransport interface. The serial interface with a variable bitrate allows the SledgeHammer to attain a data transfer rate of 3.2 GB/s - in both directions simultaneously. This results in a total bandwidth of 6.4 GB/s. By comparison, the Pentium 4 with 533 MHz FSB allows a maximum data throughput of 3.97 GB/s - but not in both directions simultaneously. The bandwidth of the serial interface is designed to be flexible. AMD gives the server version of the Hammer three HyperTransport ports. The entire data traffic of the Hammer processor runs through the HyperTransport interface and the integrated memory controller. In order to let the neighboring CPU gain direct access to its system memory, the Hammer uses the XBAR switch. For commands and addresses, the XBAR switch has further 64-bit buses available.